High-speed C-testable systolic array design for Galois-field inversion
نویسندگان
چکیده
Systolic architectures for inversion in Galois eld (GF (2)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.
منابع مشابه
Efficient Bit - Parallel Systolic Multiplier over GF ( 2 m )
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